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semiconductor group 1 5.96 ? 1 048 576 words by 4-bit organization ? 0 to 70 ?c operating temperature ? hyper page mode - edo ? performance: ? single + 5 v ( 10 %) supply ? low power dissipation max. 660 mw active (-50 version) max. 605 mw active (-60 version) max. 550 mw active (-70 version) ? standby power dissipation: 11 mw max.standby (ttl) 5.5 mw max.standby (cmos) 1.1 mw max.standby (cmos) for low power version ? read, write, read-modify write, cas-before- ras refresh, ras-only refresh, hidden refresh and test mode capability ? all inputs and outputs ttl-compatible ? 1024 refresh cycles / 16 ms ? 1024 refresh cycles / 128 ms for low power version ? plastic packages: p-soj-26/20-5 with 300 mil width -50 -60 -70 t rac ras access time 50 60 70 ns t cac cas access time 13 15 20 ns t aa access time from address 25 30 35 ns t rc read/write cycle time 89 104 124 ns t hpc hyper page mode (edo) cycle time 20 25 30 ns 1m x 4-bit dynamic ram (hyper page mode (edo) version) preliminary information hyb 514405bj/bjl-50/-60/-70
semiconductor group 2 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram the hyb 514405bj is the new generation dynamic ram organized as 1 048 576 words by 4-bit. the hyb 514405bj utilizes cmos silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. multiplexed address inputs permit the hyb 514405bj to be packed in a standard plastic p-soj-26/20 package. this package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. system oriented feature include single + 5 v ( 10 %) power supply, direct interfacing with high performance logic device families. ordering information type ordering code package descriptions hyb 514405bj-50 q67100-q2116 p-soj-26/20-5 edo-dram (access time 50 ns) hyb 514405bj-60 q67100-q2118 p-soj-26/20-5 edo-dram (access time 60 ns) hyb 514405bj-70 q67100-q2120 p-soj-26/20-5 edo-dram (access time 70 ns) hyb 514405bjl-50 on request p-soj-26/20-5 low power edo-dram (access time 50 ns) hyb 514405bjl-60 on request p-soj-26/20-5 low power edo-dram (access time 60 ns) hyb 514405bjl-70 on request p-soj-26/20-5 low power edo-dram (access time 70 ns)
semiconductor group 3 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram pin configuration (top view) pin names a0-a9 address input ras row address strobe cas column address strobe we read/write input oe output enable i/ o1 - i/ o4 data input/output v cc power supply (+ 5 v) v ss ground (0 v) n.c. no connection p-soj-26/20-5
semiconductor group 4 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram block diagram
semiconductor group 5 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram absolute maximum ratings operating temperature range ............................................................................................0 to 70 ?c storage temperature range......................................................................................C 55 to + 150 ?c input/output voltage ........................................................................................................ C 1 to + 7 v power supply voltage ..................................................................................................... C 1 to + 7 v data out current (short circuit) ................................................................................................ 50 ma note: stresses above those listed under "absolute maximum ratings" may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 ?c, v ss = 0 v, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit test condition min. max. input high voltage v ih 2.4 v cc + 0.5 v 1) input low voltage v il C 1.0 0.8 v 1) output high voltage ( i out = C 5 ma) v oh 2.4 C v 1) output low voltage ( i out = 4.2 ma) v ol C 0.4 v 1) input leakage current, any input (0 v < v in < 7, all other input = 0 v) i i(l) C 10 10 m a 1) output leakage current (do is disabled, 0 < v out < v cc ) i o(l) C 10 10 m a 1) average v cc supply current -50 version -60 version -70 version i cc1 C C C 120 110 100 ma 2) 3)4) standby v cc supply current ( ras = cas = we = v ih ) i cc2 C2maC average v cc supply current during ras-only refresh cycles -50 version -60 version -70 version i cc3 C C C 120 110 100 ma 2)4) average v cc supply current during hyper page mode(edo) operation -50 version -60 version -70 version i cc4 C C C 100 90 80 ma 2) 3)4) standby v cc supply current ( ras = cas = we = v cc C 0.2 v) i cc5 C1 200 ma m a 1) l-version
semiconductor group 6 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram average v cc supply current during cas before ras refresh mode -50 version -60 version -70 version i cc6 C C C 120 110 100 ma 2)4) for low power version only: battery backup current (average power supply current in battery backup mode): ( cas = cas before ras cycling or 0.2 v, we = v cc C 0.2 v or 0.2 v, a0 to a10 = v cc C 0.2 v or 0.2 v; d i = v cc C 0.2 v or 0.2 v or open, t rc = 125 m s, t ras = t ras min = 1 m s) i cc7 C 250 m aC ac characteristics 5)6) t a = 0 to 70 ?c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max. common parameters random read or write cycle time t rc 89 C 104 C 124 C ns ras precharge time t rp 35 C 40 C 50 C ns ras pulse width t ras 50 10k 60 10k 70 10k ns cas pulse width t cas 8 10k 10 10k 12 10k ns row address setup time t asr 0C0C0Cns row address hold time t rah 8C10C10Cns column address setup time t asc 0C0C0Cns column address hold time t cah 8C10C12Cns ras to cas delay time t rcd 12 37 14 45 14 53 ns ras to column address delay time t rad 10 25 12 30 12 35 ns ras hold time t rsh 13 15 C 17 C ns dc characteristics (contd) t a = 0 to 70 ?c, v ss = 0 v, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit test condition min. max.
semiconductor group 7 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram cas hold time t csh 50 60 C 70 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 150150150ns7 refresh period t ref C16C16C16ms refresh period for l-version t ref C 128 C 128 C 128 ms read cycle access time from ras t rac C 50 C 60 C 70 ns 8, 9 access time from cas t cac C 13 C 15 C 17 ns 8, 9 access time from column address t aa C 25 C 30 C 35 ns 8,10 oe access time t oea C13C15C17ns column address to ras lead time t ral 25 C 30 C 35 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns11 read command hold time referenced to ras t rrh 0C0C0Cns11 cas to output in low-z t clz 0C0C0Cns8 output buffer turn-off delay t off 013015017ns12 output buffer turn-off delay from oe t oez 013015017ns12 data to cas low delay t dzc 0C0C0Cns13 data to oe low delay t dzo 0C0C0Cns13 cas high to data delay t cdd 10 C 13 C 15 C ns 14 oe high to data delay t odd 10 C 13 C 15 C ns 14 write cycle write command hold time t wch 8C10C10Cns write command pulse width t wp 8C10C10Cns write command setup time t wcs 0C0C0Cns15 ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 8 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram write command to ras lead time t rwl 13 C 15 C 17 C ns write command to cas lead time t cwl 13 C 15 C 17 C ns data setup time t ds 0C0C0Cns16 data hold time t dh 8C10C12Cns16 read-modify-write cycle read-write cycle time t rwc 118 C 138 C 162 C ns ras to we delay time t rwd 64 C 77 C 89 C ns 15 cas to we delay time t cwd 27 C 32 C 36 C ns 15 column address to we delay time t awd 39 C 47 C 54 C ns 15 oe command hold time t oeh 10 C 13 C 15 C ns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 20 C 25 C 30 C ns cas precharge time t cp 8C10C10Cns access time from cas precharge t cpa C27C32C37ns7 output data hold time t coh 5C5C5Cns ras pulse width in hyper page mode t ras 50 200k 60 200k 70 200k ns cas precharge to ras delay t rhcp 27 C 32 C 37 C ns hyper page mode (edo) read- modify-write cycle hyper page mode (edo) read- write cycle time t prwc 58 C 68 C 77 C ns cas precharge to we t cpwd 41 C 49 C 56 C ns ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 9 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram cas before ras refresh cycle cas setup time t csr 10 C 10 C 10 C ns cas hold time t chr 10 C 10 C 10 C ns ras to cas precharge time t rpc 5C5C5Cns write to ras precharge time t wrp 10 C 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C 10 C ns cas-before-ras counter test cycle cas precharge time ( cas- before- ras counter test cycle) t cpt 35 C 40 C 40 C ns test mode write command setup time t wts 10 C 10 C 10 C ns write command hold time t wth 10 C 10 C 10 C ns capacitance t a = 0 to 70 ?c; v cc = 5 v 10 %; f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a9) c i1 C5pf input capacitance ( ras, cas, we, oe) c i2 C7pf output capacitance ( i o1 to i o4) c io C7pf ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 5 v 10 %, t t = 2 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 10 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram notes: 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4) address can be changed once or less while ras = v il . in case of i cc4 it can be changed once or less during a hyper page mode (edo) cycle 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume t t = 2 ns. 7) v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 8) measured with the specified current load and 100 pf at v ol = 0.8 v and v oh = 2.0 v. access time is determined by the latter of t rac , t cac , t aa , t cpa , t oea . t cac is measured from tristate. 9) operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10) operation within the t rad (max. ) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11) either t rch or t rrh must be satisfied for a read cycle. 12) t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas, whichever occurs last. 13) either t dzc or t dzo must be satisfied. 14) either t cdd or t odd must be satisfied. 15) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16) these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles.
semiconductor group 11 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram read cycle
semiconductor group 12 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram write cycle (early write)
semiconductor group 13 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram write cycle ( oe controlled write)
semiconductor group 14 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram read-write (read-modify-write) cycle
semiconductor group 15 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram hyper page mode (edo) read cycle
semiconductor group 16 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram hyper page mode (edo) early write cycle
semiconductor group 17 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram hyper page mode (edo) late write cycle
semiconductor group 18 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram hyper page mode (edo) read-modify-write cycle
semiconductor group 19 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram ras-only refresh cycle
semiconductor group 20 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram cas-before- ras refresh cycle
semiconductor group 21 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram hidden refresh cycle (read)
semiconductor group 22 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram hidden refresh cycle (early write)
semiconductor group 23 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram cas-before- ras refresh counter test cycle
semiconductor group 24 hyb 514405bj/blj-50/-60/-70 1m x 4 edo - dram test mode entry
semiconductor group 25 hyb 514405bj/bjl-50/-60/-70 1m x 4 edo - dram test mode as the hyb 514405bj/bt is organized internally as 512k x 8-bits, a test mode cycle using 8:1 compression can be used to improve test time. note that in the 1m x 4 version the test time is reduced by 1/2 for a linear test pattern. in a test mode write the data from each i/o1 pin is written into eight bits simultaneously (all 1 s or all 0 s).the i/o2-i/o4 inputs are not used for writing in test mode. in test mode read each i/o output is used for indicating the test mode result. if the internal eight bits are equal, the i/o would indicate a 1. if they were not equal, the i/o would indicate a 0.note that in test mode ?read i/o1- i/o3 are always driven to ?ones ,i.e. all outputs will be ?1s for a test mode ?pass. the wcbr cycle ( we, cas before ras) puts the device into test mode. to exit from test mode, a cas before ras refresh, ras only refresh or hidden refresh can be used. addresses a10r, a10c and a0c are dont care during test mode. package outlines p-soj-26/20-5 (small outline j-leaded package) gpj05627 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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